1. Field of the Invention
The present invention relates to a semiconductor integrated circuit.
2. Description of the Background Art
Current supply capability of a booster circuit embedded in a non-volatile memory is extremely low, and a generated high voltage is not resistant to noise or the like. As such, the generated high voltage cannot be output to an external terminal. In such a situation, Japanese Patent Laying-Open No. 5-325580 discloses a technology to check an internal voltage by embedding an A/D (analog/digital) converter for a test, dividing the generated high voltage for conversion by the A/D converter so as to output a resultant digital signal to the outside, and monitoring the digital signal.
On the other hand, integration on a chip of an A/D converter dedicated for a test in order to check an internally generated voltage leads to an increase in a chip area, which is not advantageous in terms of cost.
Recently, a circuit size of a semiconductor integrated circuit has increased as the development of system-on-chip, and accordingly, an increase in the number of man-hours in a mass production shipment test as well as in design verification has been an issue.
In particular in a semiconductor integrated circuit on which a voltage down converter (VDC) and the A/D converter are integrated, design evaluation and mass production test for the voltage down converter, the A/D converter and other logic circuits are currently performed for each individual circuit.
In evaluating whether or not an output voltage of a VDC circuit follows a designed value, or in testing whether or not a voltage output by the VDC circuit is normal in a mass production shipment test, an output voltage VDCout of the VDC circuit needs be provided and measured as an analog value from a terminal of the semiconductor integrated circuit. Therefore, a measurement system has been complicated.
In addition, circuit size of the individual circuit has increased, which leads to an increase in the number of man-hours in mass production test and design evaluation. Moreover, the number of input/output terminals of these semiconductor integrated circuits has increased, and an area for arranging input/output pads is not negligible, considering the chip size of the semiconductor integrated circuit. In particular, when the number of input/output pads increases, the chip size is determined by arrangement of the pads in a peripheral area, not by the size of the circuit arranged in an inner area.